#include "driver_config.h"
#include "target_config.h"

#include "gpio.h"
#include "timer322.h"
#include "ssp.h"
#include "RFM70.h"
#include "timer162.h"

//      sending to RFM70 MSB first

//Banks1 registers which must be writen
//0-8;  Byte(MSB->LSB), Bit(MSB->LSB)
const u8 Bank1_Reg00[] = { 0x40, 0x4B, 0x01, 0xE2 };
const u8 Bank1_Reg01[] = { 0xC0, 0x4B, 0x00, 0x00 };
const u8 Bank1_Reg02[] = { 0xD0, 0xFC, 0x8C, 0x02 };
const u8 Bank1_Reg03[] = { 0x99, 0x00, 0x39, 0x41 };
const u8 Bank1_Reg04[] = { 0xD9, 0x9E, 0x86, 0x0B };
const u8 Bank1_Reg05[] = { 0x24, 0x06, 0x7F, 0xA6 };
//12-14;    Byte(LSB->MSB), Bit(MSB->LSB)
const u8 Bank1_Reg0C[] = { 0x00, 0x12, 0x73, 0x00 };
const u8 Bank1_Reg0D[] = { 0x36, 0xB4, 0x80, 0x00 };
const u8 Bank1_Reg0E[] = { 0x41, 0x20, 0x08, 0x04, 0x81, 0x20, 0xCF, 0xF7, 0xFE, 0xFF, 0xFF };

//Initializing values of Bank0 registres
const u8 Bank0_Reg[][2] = { { 0x00, 0x0F },//  0CONFIG //  reflect RX_DR\TX_DS\MAX_RT,Enable CRC ,2byte,POWER UP,PRX
		{ 0x01, 0x3F },//  1EN_AA      //  Enable auto acknowledgement data pipe5\4\3\2\1\0
		{ 0x02, 0x3F },//  2EX_RXADDR  //  Enable RX Addresses pipe5\4\3\2\1\0
		{ 0x03, 0x03 },//  3SETUP_AW   //RX/TX address field width 5byte
		{ 0x04, 0xff },//  4SETUP_RETR //auto retransmission dalay (4000us),auto retransmission count(15)
		{ 0x05, 0x17 },//  5RF_CH  //  23 channel
		{ 0x06, 0x17 },//  6RF_SETUP   //air data rate-1M,out power 0dbm,setup LNA gain
		{ 0x07, 0x07 },//  7STATUS //
		{ 0x08, 0x00 },//  8OBSERVER_TX    //
		{ 0x09, 0x00 },//  9CD //
		{ 0x0C, 0xc3 },//  10RX_ADDR_P2    //  only LSB Receive address data pipe 2, MSB bytes is equal to RX_ADDR_P1[39:8]
		{ 0x0D, 0xc4 },//  11RX_ADDR_P3    //  only LSB Receive address data pipe 3, MSB bytes is equal to RX_ADDR_P1[39:8]
		{ 0x0E, 0xc5 },//  12RX_ADDR_P4    //  only LSB Receive address data pipe 4, MSB bytes is equal to RX_ADDR_P1[39:8]
		{ 0x0F, 0xc6 },//  13RX_ADDR_P5    //  only LSB Receive address data pipe 5, MSB bytes is equal to RX_ADDR_P1[39:8]
		{ 0x11, 0x20 },//  14RX_PW_P0  //  Number of bytes in RX payload in data pipe0(32 byte)
		{ 0x12, 0x20 },//  15RX_PW_P1  //  Number of bytes in RX payload in data pipe1(32 byte)
		{ 0x13, 0x20 },//  16RX_PW_P2  //  Number of bytes in RX payload in data pipe2(32 byte)
		{ 0x14, 0x20 },//  17RX_PW_P3  //  Number of bytes in RX payload in data pipe3(32 byte)
		{ 0x15, 0x20 },//  18RX_PW_P4  //  Number of bytes in RX payload in data pipe4(32 byte)
		{ 0x16, 0x20 },//  19RX_PW_P5  //  Number of bytes in RX payload in data pipe5(32 byte)
		{ 0x17, 0x00 },//  20FIFO_STATUS   //  fifo status
		{ 0x1C, 0x3F },//  21DYNPD //  Enable dynamic payload length data pipe5\4\3\2\1\0
		{ 0x1D, 0x07 }//   22FEATURE   //  Enables Dynamic Payload Length,Enables Payload with ACK,Enables the W_TX_PAYLOAD_NOACK command
};
//Address = Bank1_Reg0A pipe 0 & Bank1_Reg0B pipe 1; in Bank 0
const u8 RX0_Address[] = { 0xE7, 0xE7, 0xE7, 0xE7, 0xE7 };//Receive address data pipe 0 -> default value
const u8 RX1_Address[] = { 0xC2, 0xC2, 0xC2, 0xC2, 0xC2 };//Receive address data pipe 1 -> default value

extern u8 rx_buf[MAX_PACKET_LEN];

extern void delay_200ms(void);
extern void delay_50ms(void);

u8 status;

u8 SPI_R(void)
{
	LPC_SSP0->DR = 0xFF;
	while ( (LPC_SSP0->SR & (SSPSR_BSY|SSPSR_RNE)) != SSPSR_RNE );
	return LPC_SSP0->DR;
}
void SPI_W(u8 value)	// OK
{
	  while ( (LPC_SSP0->SR & (SSPSR_TNF|SSPSR_BSY)) != SSPSR_TNF );
	  LPC_SSP0->DR = value;
	  while ( (LPC_SSP0->SR & (SSPSR_BSY|SSPSR_RNE)) != SSPSR_RNE );
	  status = LPC_SSP0->DR;
}

/**************************************************
Function: CSN_Low(); CSN_High();
/**************************************************/
void CSN_Low(void){	GPIOSetValue(PORT0, 2, 0);}
void CSN_High(void){GPIOSetValue(PORT0, 2, 1);}

/**************************************************
Function: CE_Low(); CE_High();
/**************************************************/
void CE_Low(void){	GPIOSetValue(PORT0, 7, 0);}
void CE_High(void){	GPIOSetValue(PORT0, 7, 1);}


void SPI_Command(RFM70_Commands_TypeDef cmd) {
	CSN_Low(); // CSN low, init SPI transaction
	SPI_W(cmd); // Do cmd
	CSN_High(); // CSN high again, end SPI transaction
}

void SPI_Write_Reg(RFM70_RWReg_TypeDef write, RFM70_RegAddr_TypeDef addr,
		u8 value) {
	CSN_Low(); // CSN low, init SPI transaction
	SPI_W(write | addr); // select register
	SPI_W(value); // ..and write value to it..
	CSN_High(); // CSN high again, end SPI transaction
}


u8 SPI_Read_Reg(RFM70_RegAddr_TypeDef addr) {
	u8 value;

	CSN_Low(); // CSN low, initialize SPI transaction
	SPI_W(addr); // Select register to read from.
	value = SPI_R(); // ..then read register value
	CSN_High(); // CSN high, terminate SPI communication

	return (value); // return register value
}

void SPI_Read_Buf(u8 reg, u8 *pBuf, u8 length) {
	u8 byte_ctr;

	CSN_Low();
	SPI_W(reg); // Select register to write, and read status u8
	for (byte_ctr = 0; byte_ctr < length; byte_ctr++)
		pBuf[byte_ctr] = SPI_R(); // Perform SPI_RW to read u8 from RFM70
	CSN_High(); // Set CSN high again
}

void SPI_Write_Buf(RFM70_RWReg_TypeDef RW, RFM70_RegAddr_TypeDef addr,
		u8 *pBuf, u8 length) {
	u8 byte_ctr;

	CSN_Low(); // Set CSN low, init SPI tranaction
	SPI_W(RW | addr); // Select register to write to and read status u8
	for (byte_ctr = 0; byte_ctr < length; byte_ctr++) // then write all u8 in buffer(*pBuf)
		SPI_W(*pBuf++);
	CSN_High(); // Set CSN high again

}

void SPI_Activate(RFM70_CommandsW_Typedef activate, u8 cmd) {
	CSN_Low();
	SPI_W(activate);
	SPI_W(cmd);
	CSN_High();
}

void SPI_Write_Ini_Buf(RFM70_RWReg_TypeDef RW, RFM70_RegAddr1_TypeDef addr,
		u8 *pBuf, u8 length) {
	u8 byte_ctr;

	CSN_Low(); // Set CSN low, init SPI tranaction
	SPI_W(RW | addr); // Select register to write to and read status u8
	for (byte_ctr = 0; byte_ctr < length; byte_ctr++) // then write all u8 in buffer(*pBuf)
		SPI_W(*pBuf++);
	CSN_High(); // Set CSN high again

}

void RFM70_SwitchToRxMode() {
	u8 value;

	SPI_Command(FLUSH_RX);//flush Rx
	value = SPI_Read_Reg(STATUS); // read register STATUS's value
	SPI_Write_Reg(WRITE_REG, STATUS, value);// clear RX_DR or TX_DS or MAX_RT interrupt flag
	CE_Low();
	value = SPI_Read_Reg(CONFIG); // read register CONFIG's value
	//PRX
	value = value | 0x01;
	SPI_Write_Reg(WRITE_REG, CONFIG, value); // Set PWR_UP bit, enable CRC(2 length) & Prim:RX. RX_DR enabled..
	CE_High();
}

void RFM70_SwitchToTxMode() {
	u8 value;
	SPI_Command(FLUSH_TX);//flush Tx
	CE_Low();
	value = SPI_Read_Reg(CONFIG); // read register CONFIG's value
	//PTX
	value = value & 0xfe; //  mask all bits without first / switch to PTX
	SPI_Write_Reg(WRITE_REG, CONFIG, value); // Set PWR_UP bit, enable CRC(2 length) & Prim:RX. RX_DR enabled.
	CE_High();
}

void SwitchCFG(char _cfg)//1:Bank1 0:Bank0
{
	u8 Tmp;

	Tmp = SPI_Read_Reg(STATUS); //Read the STATUS register
	Tmp = Tmp & 0x80; //Mask only the RBANK bit
	if (((Tmp) && (_cfg == 0)) || (((Tmp) == 0) && (_cfg))) //If bank isn't the same that is required, change it
	{
		SPI_Activate(ACTIVATE_CMD, 0x53); //sending the required command
	}
}

void SetChannelNum(u8 channel) {
	SPI_Write_Reg(WRITE_REG, RF_CH, channel); // Write the channel number which works on the RFM70
}

void Send_Packet(RFM70_TRx_TypeDef type, u8* pbuf, u8 len) {
	u8 fifo_sta;

	fifo_sta = SPI_Read_Reg(FIFO_STATUS); // read register FIFO_STATUS's value
	if ((fifo_sta & FIFO_STATUS_TX_FULL) == 0)//if not full, send data (write buff)
	{
		SPI_Write_Buf(WRITE_REG, type, pbuf, len); // Writes data to buffer
	}
}

void Receive_Packet(u8 *rx_buf) {
	u8 len, i, sta, fifo_sta;
	//u8 rx_buf[MAX_PACKET_LEN];
	for (i = 0; i < MAX_PACKET_LEN; i++)
		rx_buf[i] = 0; // writing zeros to rx_buf
	sta = SPI_Read_Reg(STATUS); // read register STATUS's value

	if ((STATUS_RX_DR & sta) == 0x40) // if receive data ready (RX_DR) interrupt
	{
		do {
			len = SPI_Read_Reg(R_RX_PL_WID_CMD); // read length of recived packet

			if (len <= MAX_PACKET_LEN) {
				SPI_Read_Buf(RD_RX_PLOAD, rx_buf, len);// read receive payload from RX_FIFO buffer
			} else {
				SPI_Command(FLUSH_RX); //  bad data reviced - flush Rx
			}

			fifo_sta = SPI_Read_Reg(FIFO_STATUS); // read register FIFO_STATUS's value

		} while ((fifo_sta & FIFO_STATUS_RX_EMPTY) == 0); //while not empty
	}
	SPI_Write_Reg(WRITE_REG, STATUS, sta);// clear RX_DR or TX_DS or MAX_RT interrupt flag
}

void Ini_Bank0() {
	u8 i, j; // j-counter, i-variable
	u8 WriteArr[12];

	SwitchCFG(0); //switch to bank0

	for (j = 0; j < 23; j++) //initialize RFM70 - REGISTERS
	{
		SPI_Write_Reg(WRITE_REG, Bank0_Reg[j][0], Bank0_Reg[j][1]);
	}

	for (j = 0; j < 5; j++) //initialize RFM70 - PIPES (RX0)
	{
		WriteArr[j] = RX0_Address[j];
	}
	SPI_Write_Buf(WRITE_REG, RX_ADDR_P0, &(WriteArr[0]), 5);

	for (j = 0; j < 5; j++) //initialize RFM70 - PIPES (RX1)
	{
		WriteArr[j] = RX1_Address[j];
	}
	SPI_Write_Buf(WRITE_REG, RX_ADDR_P1, &(WriteArr[0]), 5);

	for (j = 0; j < 5; j++) // initialize RFM70 - TX_ADDR
	{
		WriteArr[j] = RX0_Address[j];
	}
	SPI_Write_Buf(WRITE_REG, TX_ADDR, &(WriteArr[0]), 5);

	i = SPI_Read_Reg(FEATURE);
	if (i == 0) // i!=0 showed that chip has been actived.so do not active again.
		SPI_Activate(ACTIVATE_CMD, 0x73); // Activate
	for (j = 22; j >= 21; j--) {
		SPI_Write_Reg(WRITE_REG, Bank0_Reg[j][0], Bank0_Reg[j][1]); // Reinitialize the start value of DYNPD and FEATURE
	}
}
void Ini_Bank1() {
	u8 j;
	u8 WriteArr[12];

	SwitchCFG(1);
	//  reg:00
	for (j = 0; j < 4; j++) {
		WriteArr[j] = Bank1_Reg00[j];
	}
	SPI_Write_Ini_Buf(WRITE_REG, A_00, &(WriteArr[0]), 4);
	//  reg:01
	for (j = 0; j < 4; j++) {
		WriteArr[j] = Bank1_Reg01[j];
	}
	SPI_Write_Ini_Buf(WRITE_REG, A_01, &(WriteArr[0]), 4);
	//  reg:02
	for (j = 0; j < 4; j++) {
		WriteArr[j] = Bank1_Reg02[j];
	}
	SPI_Write_Ini_Buf(WRITE_REG, A_02, &(WriteArr[0]), 4);
	//  reg:03
	for (j = 0; j < 4; j++) {
		WriteArr[j] = Bank1_Reg03[j];
	}
	SPI_Write_Ini_Buf(WRITE_REG, A_03, &(WriteArr[0]), 4);
	//  reg:04
	for (j = 0; j < 4; j++) {
		WriteArr[j] = Bank1_Reg04[j];
	}
	SPI_Write_Ini_Buf(WRITE_REG, A_04, &(WriteArr[0]), 4);
	//  reg:05
	for (j = 0; j < 4; j++) {
		WriteArr[j] = Bank1_Reg05[j];
	}
	SPI_Write_Ini_Buf(WRITE_REG, A_05, &(WriteArr[0]), 4);
	//  reg:0C
	for (j = 0; j < 4; j++) {
		WriteArr[j] = Bank1_Reg0C[j];
	}
	SPI_Write_Ini_Buf(WRITE_REG, A_0C, &(WriteArr[0]), 4);
	//  reg:0D
	for (j = 0; j < 4; j++) {
		WriteArr[j] = Bank1_Reg0D[j];
	}
	SPI_Write_Ini_Buf(WRITE_REG, A_0D, &(WriteArr[0]), 4);
	//  reg:0E
	for (j = 0; j < 11; j++) {
		WriteArr[j] = Bank1_Reg0E[j];
	}
	SPI_Write_Ini_Buf(WRITE_REG, A_0E, &(WriteArr[0]), 11);
}

void RFM70_Initialize() {

	delay_200ms(); //delay more than 50ms.

	Ini_Bank0();
	Ini_Bank1();
	delay_50ms();
	SwitchCFG(0); //switch back to Bank0 register access
}

void DelayMs(int ms) {
	delay32Ms(0,1);
}

void delay_200ms(void) {
	delay32Ms(0,200);
}

void delay_50ms(void) {
	delay32Ms(0,50);
}


///* ****************************************************************************/
///*																			 PWr																	*/
///*																	 01-12-2010r															*/
///*																																						*/
///*												Program Grzegorza Ko�odziejczyka										*/
///*													  		  RFM70 - library														*/
///*													 uC STM8s - RFM70 (2,4 GHz)										    */
///*																		ver. 1.0															  */
///*																  							     												*/
///*																																						*/
///* ****************************************************************************/
//
//#include "driver_config.h"
//#include "target_config.h"
//
//#include "gpio.h"
//#include "timer322.h"
//#include "ssp.h"
//#include "RFM70.h"
//#include "timer162.h"
//
///***********************************************
///*		sending to RFM70 MSB first
///**********************************************/
//
////Banks1 registers which must be writen
////0-8;	Byte(MSB->LSB), Bit(MSB->LSB)
//const u8 Bank1_Reg00[]={0x40,0x4B,0x01,0xE2};
//const u8 Bank1_Reg01[]={0xC0,0x4B,0x00,0x00};
//const u8 Bank1_Reg02[]={0xD0,0xFC,0x8C,0x02};
//const u8 Bank1_Reg03[]={0x99,0x00,0x39,0x41};
//const u8 Bank1_Reg04[]={0xD9,0x9E,0x86,0x0B};
//const u8 Bank1_Reg05[]={0x24,0x06,0x7F,0xA6};
////12-14;	Byte(LSB->MSB), Bit(MSB->LSB)
//const u8 Bank1_Reg0C[]={0x00,0x12,0x73,0x00};
//const u8 Bank1_Reg0D[]={0x36,0xB4,0x80,0x00};
//const u8 Bank1_Reg0E[]={0x41,0x20,0x08,0x04,0x81,0x20,0xCF,0xF7,0xFE,0xFF,0xFF};
//
////Initializing values of Bank0 registres
//const u8 Bank0_Reg[][2]={
//{0x00,0x0F},//	0CONFIG	//	reflect RX_DR\TX_DS\MAX_RT,Enable CRC ,2byte,POWER UP,PRX
//{0x01,0x3F},//	1EN_AA		//	Enable auto acknowledgement data pipe5\4\3\2\1\0
//{0x02,0x3F},//	2EX_RXADDR	//	Enable RX Addresses pipe5\4\3\2\1\0
//{0x03,0x03},//	3SETUP_AW	//RX/TX address field width 5byte
//{0x04,0xff},//	4SETUP_RETR	//auto retransmission dalay (4000us),auto retransmission count(15)
//{0x05,0x17},//	5RF_CH	//	23 channel
//{0x06,0x17},//	6RF_SETUP	//air data rate-1M,out power 0dbm,setup LNA gain
//{0x07,0x07},//	7STATUS	//
//{0x08,0x00},//	8OBSERVER_TX	//
//{0x09,0x00},//	9CD	//
//{0x0C,0xc3},//	10RX_ADDR_P2	//	only LSB Receive address data pipe 2, MSB bytes is equal to RX_ADDR_P1[39:8]
//{0x0D,0xc4},//	11RX_ADDR_P3	//	only LSB Receive address data pipe 3, MSB bytes is equal to RX_ADDR_P1[39:8]
//{0x0E,0xc5},//	12RX_ADDR_P4	//	only LSB Receive address data pipe 4, MSB bytes is equal to RX_ADDR_P1[39:8]
//{0x0F,0xc6},//	13RX_ADDR_P5	//	only LSB Receive address data pipe 5, MSB bytes is equal to RX_ADDR_P1[39:8]
//{0x11,0x20},//	14RX_PW_P0	//	Number of bytes in RX payload in data pipe0(32 byte)
//{0x12,0x20},//	15RX_PW_P1	//	Number of bytes in RX payload in data pipe1(32 byte)
//{0x13,0x20},//	16RX_PW_P2	//	Number of bytes in RX payload in data pipe2(32 byte)
//{0x14,0x20},//	17RX_PW_P3	//	Number of bytes in RX payload in data pipe3(32 byte)
//{0x15,0x20},//	18RX_PW_P4	//	Number of bytes in RX payload in data pipe4(32 byte)
//{0x16,0x20},//	19RX_PW_P5	//	Number of bytes in RX payload in data pipe5(32 byte)
//{0x17,0x00},//	20FIFO_STATUS	//	fifo status
//{0x1C,0x3F},//	21DYNPD	//	Enable dynamic payload length data pipe5\4\3\2\1\0
//{0x1D,0x07}//	22FEATURE	//	Enables Dynamic Payload Length,Enables Payload with ACK,Enables the W_TX_PAYLOAD_NOACK command
//};
////Address = Bank1_Reg0A pipe 0 & Bank1_Reg0B pipe 1; in Bank 0
//const u8 RX0_Address[]={0xE7,0xE7,0xE7,0xE7,0xE7};//Receive address data pipe 0	-> default value
//const u8 RX1_Address[]={0xC2,0xC2,0xC2,0xC2,0xC2};//Receive address data pipe 1 -> default value
//
///*******************************************************************/
///*******************************************************************/
//
//extern u8 rx_buf[MAX_PACKET_LEN];
//
//extern void delay_200ms(void){
//	delay32Ms(0,200);
//}
//extern void delay_50ms(void){
//	delay32Ms(0,50);
//}
//
//u8 status;
//
///**************************************************
//Function: SPI_R/W(void);
///**************************************************/
//u8 SPI_R(void)
//{
//	LPC_SSP0->DR = 0xFF;
//	while ( (LPC_SSP0->SR & (SSPSR_BSY|SSPSR_RNE)) != SSPSR_RNE );
//	return LPC_SSP0->DR;
//}
//void SPI_W(u8 value)	// OK
//{
//	  while ( (LPC_SSP0->SR & (SSPSR_TNF|SSPSR_BSY)) != SSPSR_TNF );
//	  LPC_SSP0->DR = value;
//	  while ( (LPC_SSP0->SR & (SSPSR_BSY|SSPSR_RNE)) != SSPSR_RNE );
//	  status = LPC_SSP0->DR;
//}
//
///**************************************************
//Function: CSN_Low(); CSN_High();
///**************************************************/
//void CSN_Low(void){	GPIOSetValue(PORT0, 2, 0);}
//void CSN_High(void){GPIOSetValue(PORT0, 2, 1);}
//
///**************************************************
//Function: CE_Low(); CE_High();
///**************************************************/
//void CE_Low(void){	GPIOSetValue(PORT0, 7, 0);}
//void CE_High(void){	GPIOSetValue(PORT0, 7, 1);}
//
//void SPI_Command(RFM70_Commands_TypeDef cmd)
//{
//	CSN_Low();	// CSN low, init SPI transaction
//	SPI_W(cmd);	// Do cmd
//	CSN_High();	// CSN high again, end SPI transaction
//}
///**************************************************
//Function: SPI_Write_Reg();
//
//Description:
//	Writes value 'value' to register 'reg'
///**************************************************/
//void SPI_Write_Reg(RFM70_RWReg_TypeDef write,RFM70_RegAddr_TypeDef addr, u8 value)
//{
//	CSN_Low();	// CSN low, init SPI transaction
//	SPI_W(write|addr);	// select register
//	SPI_W(value);	// ..and write value to it..
//	CSN_High();	// CSN high again, end SPI transaction
//}
//
///**************************************************
//Function: SPI_Read_Reg();
//
//Description:
//	Read one u8 from RFM70 register, 'reg'
///**************************************************/
//u8 SPI_Read_Reg(RFM70_RegAddr_TypeDef addr)
//{
//	u8 value;
//
//	CSN_Low();	// CSN low, initialize SPI transaction
//	SPI_W(addr);	// Select register to read from.
//	value = SPI_R();	// ..then read register value
//	CSN_High();	// CSN high, terminate SPI communication
//
//	return(value);	// return register value
//}
///**************************************************/
//
///**************************************************
//Function: SPI_Read_Buf();
//
//Description:
//	Reads 'length' #of length from register 'reg'
///**************************************************/
//void SPI_Read_Buf(u8 reg, u8 *pBuf, u8 length)
//{
//	u8 status,byte_ctr;
//
//	CSN_Low();
//	SPI_W(reg);	// Select register to write, and read status u8
//	for(byte_ctr=0;byte_ctr<length;byte_ctr++)
//		pBuf[byte_ctr] = SPI_R();	// Perform SPI_RW to read u8 from RFM70
//	CSN_High();	// Set CSN high again
//}
///**************************************************/
//
///**************************************************
//Function: SPI_Write_Buf();
//
//Description:
//	Writes contents of buffer '*pBuf' to RFM70
///**************************************************/
//void SPI_Write_Buf(RFM70_RWReg_TypeDef RW,RFM70_RegAddr_TypeDef addr, u8 *pBuf, u8 length)
//{
//	u8 byte_ctr;
//
//	CSN_Low();	// Set CSN low, init SPI tranaction
//	SPI_W(RW|addr);	// Select register to write to and read status u8
//	for(byte_ctr=0; byte_ctr<length; byte_ctr++) // then write all u8 in buffer(*pBuf)
//		SPI_W(*pBuf++);
//	CSN_High();	// Set CSN high again
//
//}
//
///**************************************************
//Function: SPI_Activate(RFM_CommandsW_Typedef activate);
//Description:
//	Change the bank0<->bank1
///**************************************************/
//void SPI_Activate(RFM70_CommandsW_Typedef activate, u8 cmd)
//{
//	CSN_Low();
//	SPI_W(activate);
//	SPI_W(cmd);
//	CSN_High();
//}
///***********INITIALIZE FUNCTIONS***************************
//
///**************************************************
//Function: SPI_Read_Buf();
//
//Description:
//	Reads 'length' #of length from register 'reg'
///**************************************************/
//void SPI_Read_Ini_Buf(u8 reg, u8 *pBuf, u8 length)
//{
//	u8 status,byte_ctr;
//
//	CSN_Low();
//	SPI_W(reg);	// Select register to write, and read status u8
//	for(byte_ctr=0;byte_ctr<length;byte_ctr++)
//		pBuf[byte_ctr] = SPI_R();	// Perform SPI_RW to read u8 from RFM70
//	CSN_High();	// Set CSN high again
//}
///**************************************************/
//
///**************************************************
//Function: SPI_Write_Ini_Buf();
//
//Description:
//	Writes contents of buffer '*pBuf' to RFM70
///**************************************************/
//void SPI_Write_Ini_Buf(RFM70_RWReg_TypeDef RW,RFM70_RegAddr1_TypeDef addr, u8 *pBuf, u8 length)
//{
//	u8 byte_ctr;
//
//	CSN_Low();	// Set CSN low, init SPI tranaction
//	SPI_W(RW|addr);	// Select register to write to and read status u8
//	for(byte_ctr=0; byte_ctr<length; byte_ctr++) // then write all u8 in buffer(*pBuf)
//		SPI_W(*pBuf++);
//	CSN_High();	// Set CSN high again
//
//}
//
///**************************************************
//Function: SwitchToRxMode();
//Description:
//	switch to Rx mode
///**************************************************/
//void SwitchToRxMode()
//{
//	u8 value;
//
//	SPI_Command(FLUSH_RX);//flush Rx
//	value=SPI_Read_Reg(STATUS);	// read register STATUS's value
//	SPI_Write_Reg(WRITE_REG,STATUS,value);// clear RX_DR or TX_DS or MAX_RT interrupt flag
//	CE_Low();
//	value=SPI_Read_Reg(CONFIG);	// read register CONFIG's value
////PRX
//	value=value|0x01;
//  	SPI_Write_Reg(WRITE_REG, CONFIG, value); // Set PWR_UP bit, enable CRC(2 length) & Prim:RX. RX_DR enabled..
//	CE_High();
//}
//
///**************************************************
//Function: RFM70_SwitchToTxMode();
//Description:
//	switch to Tx mode
///**************************************************/
//void RFM70_SwitchToTxMode()
//{
//	u8 value;
//	SPI_Command(FLUSH_TX);//flush Tx
//	CE_Low();
//	value=SPI_Read_Reg(CONFIG);	// read register CONFIG's value
////PTX
//		value=value&0xfe;	//	mask all bits without first / switch to PTX
//  	SPI_Write_Reg(WRITE_REG, CONFIG, value); // Set PWR_UP bit, enable CRC(2 length) & Prim:RX. RX_DR enabled.
//	CE_High();
//}
//
///**************************************************
//Function: SwitchCFG();
//
//Description:
//	 access switch between Bank1 and Bank0
//
//Parameter:
//	_cfg      1:register bank1
//	          0:register bank0
//Return:
//     None
///**************************************************/
//void SwitchCFG(char _cfg)//1:Bank1 0:Bank0
//{
//	u8 Tmp;
//
//	Tmp=SPI_Read_Reg(STATUS);	//Read the STATUS register
//	Tmp=Tmp&0x80;	//Mask only the RBANK bit
//	if( ( (Tmp)&&(_cfg==0) )
//	||( ((Tmp)==0)&&(_cfg) ) )	//If bank isn't the same that is required, change it
//	{
//		SPI_Activate(ACTIVATE_CMD, 0x53);	//sending the required command
//	}
//}
//
///**************************************************
//Function: SetChannelNum();
//Description:
//	set channel number
//
///**************************************************/
//void SetChannelNum(u8 channel)
//{
//	SPI_Write_Reg(WRITE_REG,RF_CH,channel);	// Write the channel number which works on the RFM70
//}
//
///**************************************************
//Function: Send_Packet
//Description:
//	fill FIFO to send a packet
//Parameter:
//	type: WR_TX_PLOAD or  W_TX_PAYLOAD_NOACK_CMD
//	pbuf: a buffer pointer
//	len: packet length
//Return:
//	None
//**************************************************/
//void Send_Packet(RFM70_TRx_TypeDef type,u8* pbuf,u8 len)
//{
//	u8 fifo_sta;
//
//	fifo_sta=SPI_Read_Reg(FIFO_STATUS);	// read register FIFO_STATUS's value
//	if((fifo_sta&FIFO_STATUS_TX_FULL)==0)//if not full, send data (write buff)
//	{
//		//GPIO_WriteHigh(GPIOA, GPIO_PIN_4);	// RED LIGHT = 1	SYGNALIZACJA !!!
//		SPI_Write_Buf(WRITE_REG, type, pbuf, len); // Writes data to buffer
//		delay_50ms();
//		//GPIO_WriteLow(GPIOA, GPIO_PIN_4);	// RED LIGHT = 0	SYGNALIZACJA !!!
//		delay_50ms();
//	}
//}
//
//void Ini_Bank0()
//{
//	u8 i,j,temp;	// j-counter, i-variable
// 	u8 WriteArr[12];
//	u8 rx_buf_test[MAX_PACKET_LEN];
//
//	SwitchCFG(0);	//switch to bank0
//
//	for(j=0;j<23;j++)	//initialize RFM70 - REGISTERS
//	{
//		SPI_Write_Reg(WRITE_REG, Bank0_Reg[j][0], Bank0_Reg[j][1]);
//	}
//
//	for(j=0;j<5;j++)	//initialize RFM70 - PIPES (RX0)
//	{
//		WriteArr[j]=RX0_Address[j];
//	}
//	SPI_Write_Buf(WRITE_REG, RX_ADDR_P0, &(WriteArr[0]), 5);
//
//	for(j=0;j<5;j++)	//initialize RFM70 - PIPES (RX1)
//	{
//		WriteArr[j]=RX1_Address[j];
//	}
//	SPI_Write_Buf(WRITE_REG, RX_ADDR_P1, &(WriteArr[0]), 5);
//
//	for(j=0;j<5;j++)	// initialize RFM70 - TX_ADDR
//	{
//		WriteArr[j]=RX0_Address[j];
//	}
//	SPI_Write_Buf(WRITE_REG, TX_ADDR, &(WriteArr[0]), 5);
//
//	i=SPI_Read_Reg(FEATURE);
//	if(i==0) // i!=0 showed that chip has been actived.so do not active again.
//		SPI_Activate(ACTIVATE_CMD,0x73); // Activate
//	for(j=22;j>=21;j--)
//	{
//		SPI_Write_Reg(WRITE_REG, Bank0_Reg[j][0], Bank0_Reg[j][1]); // Reinitialize the start value of DYNPD and FEATURE
//	}
//}
//void Ini_Bank1()
//{
//	u8 i,j,temp;
// 	u8 WriteArr[12];
//
//	SwitchCFG(1);
////	reg:00
//	for(j=0; j<4; j++)
//	{
//		WriteArr[j]=Bank1_Reg00[j];
//	}
//	SPI_Write_Ini_Buf(WRITE_REG, A_00, &(WriteArr[0]),4);
////	reg:01
//	for(j=0; j<4; j++)
//	{
//		WriteArr[j]=Bank1_Reg01[j];
//	}
//	SPI_Write_Ini_Buf(WRITE_REG, A_01, &(WriteArr[0]),4);
////	reg:02
//	for(j=0; j<4; j++)
//	{
//		WriteArr[j]=Bank1_Reg02[j];
//	}
//	SPI_Write_Ini_Buf(WRITE_REG, A_02, &(WriteArr[0]),4);
////	reg:03
//	for(j=0; j<4; j++)
//	{
//		WriteArr[j]=Bank1_Reg03[j];
//	}
//	SPI_Write_Ini_Buf(WRITE_REG, A_03, &(WriteArr[0]),4);
////	reg:04
//	for(j=0; j<4; j++)
//	{
//		WriteArr[j]=Bank1_Reg04[j];
//	}
//	SPI_Write_Ini_Buf(WRITE_REG, A_04, &(WriteArr[0]),4);
////	reg:05
//	for(j=0; j<4; j++)
//	{
//		WriteArr[j]=Bank1_Reg05[j];
//	}
//	SPI_Write_Ini_Buf(WRITE_REG, A_05, &(WriteArr[0]),4);
////	reg:0C
//	for(j=0; j<4; j++)
//	{
//		WriteArr[j]=Bank1_Reg0C[j];
//	}
//	SPI_Write_Ini_Buf(WRITE_REG, A_0C, &(WriteArr[0]),4);
////	reg:0D
//	for(j=0; j<4; j++)
//	{
//		WriteArr[j]=Bank1_Reg0D[j];
//	}
//	SPI_Write_Ini_Buf(WRITE_REG, A_0D, &(WriteArr[0]),4);
////	reg:0E
//	for(j=0; j<11; j++)
//	{
//		WriteArr[j]=Bank1_Reg0E[j];
//	}
//	SPI_Write_Ini_Buf(WRITE_REG, A_0E, &(WriteArr[0]),11);
//}
///**************************************************/
//void RFM70_Initialize()
//{
//	delay_200ms();	//delay more than 50ms.
//
//  Ini_Bank0();
//	Ini_Bank1();
//	delay_50ms();
//	SwitchCFG(0);	//switch back to Bank0 register access
//}
//
///**************************************************
//Function: DelayMs();
//
//Description:
//	delay ms,please implement this function according to your MCU.
///**************************************************/
//void DelayMs(int ms)
//{
//	delay32Ms(1,1);
//}
